1. Field of the Invention
The present invention relates to a method for producing a Group III nitride compound semiconductor element. The invention relates to a laser lift-off technique involving epitaxially growing a Group III nitride compound semiconductor on a different kind of substrate to form an element structure, adhering a conductive supporting substrate to the top layer of the element structure through a metal or a solder or other conductive layer, and then decomposing a thin layer of the Group III nitride compound semiconductor in the vicinity of the interface with the different kind of substrate by laser irradiation to remove the different kind of substrate. The invention is particularly effective in a method for producing a Group III nitride compound semiconductor light emitting element having pn junction or having a p type layer and an n type layer one above the other with an active layer interposed therebetween.
2. Description of the Related Art
The laser lift-off technique that has been introduced first by Kelly et al. described as Non-patent Document 1 (Appl. Phys. Lett., vol 69, 1996, pp. 1749-1751) has enabled a light emitting element or a Group III nitride compound semiconductor element to re-adhere to a conductive supporting substrate from the substrate for use in epitaxial growth. This enables to provide an electrode on the rear surface of the supporting substrate in a light emitting diode. Thus, a light emitting element having positive and negative counter electrodes at two portions of the rear surface of the substrate and the top surface of the epitaxial layer similarly as a GaAs light emitting element can be obtained. Advantages obtained by providing positive and negative electrodes in such a manner as to face with each other with a light emitting layer interposed therebetween reside in that a light emitting area approximately equal to the level area of the supporting substrate can be formed and uniform light emission can be achieved, whereby light extraction efficiency per element can be increased.
FIGS. 9 and 10 are two flow charts (cross sectional views) briefly illustrating two different techniques that have been published at present. For example, an element in which an n type layer 11 and a p type layer 12 are formed in order using a different kind of substrate, such as a sapphire substrate, as an epitaxial growth substrate 100 as illustrated in FIG. 9 is taken as an example. In this description, a laminate in which the n type layer 11 and the p type layer 12 are provided, and a light emitting region L is formed among therebetween is referred to as an epitaxial layer 10. In this description, the element in which the n type layer 11 and the p type layer 12 are provided, and the light emitting region L is formed among therebetween is mentioned, but it is a matter of course that the structure of the light emitting element is not limited to such a simple structure.
On the epitaxial growth substrate 100, the n type layer 11 and the p type layer 12 are formed in order. On the p type layer 12, a contact electrode 121 and a metal or other conductive layer 122 are formed. Separately, a metal or other conductive layer 222 is formed on the surface of a conductive supporting substrate 200 containing silicon or the like. Next, on the surface of the conductive layer 122 and the surface of the conductive layer 222, a solder layer 50 is formed. Then, through the solder layers, the epitaxial growth substrate 100 on which the n type layer 11 and the p type layer 12 have been formed and the conductive supporting substrate 200 are adhered to each other. Thereafter, laser LSR is emitted to each chip, for example.
Thus, for example, the interface of a gallium nitride GaN layer facing a sapphire substrate through an aluminum nitride buffer is decomposed into a thin film, and then separated into molten metal gallium (Ga) and nitrogen (N2) gas. When the gallium nitride GaN layer is decomposed successively from the outer periphery of a wafer in which the epitaxial growth substrate 100 and the supporting substrate 200 have been joined to each other, molten metal gallium (Ga) and nitrogen (N2) gas generated by decomposition can be discharged to the outside from the outer periphery of the wafer.
FIG. 10 illustrates a technique of providing an air vent tr communicating with the outside on the outer periphery of the wafer so as to further facilitate discharge of the molten metal gallium (Ga) and nitrogen (N2) gas generated by decomposition. The air vent tr is formed by dry etching using a resist mask from the side of the p type layer 12 of the epitaxial layer before joining of the epitaxial growth substrate 100 and the supporting base 200 having the epitaxial layer 10. In this case, dry etching using a resist mask is carried out from the side of the p type layer 12, resulting in that the side surfaces of the etched outer periphery of the epitaxial layer have a taper (inclination). With respect to the taper (inclination), the horizontal cross section area of the p type layer 12 is the smallest, and the horizontal area of the light emitting region L and the n type layer 11 becomes larger in order toward the light emitting region L and the n type layer 11. In general, in the dry etching of the Group III nitride compound semiconductor using a resist mask, the taper (inclination) forms an angle of 60 to 80° with the horizontal plane. More specifically, in FIG. 10, when separated into each light emitting element chip, a reverse-tapered element in which the horizontal cross section area of the n type layer 11 which is an upper portion is larger than the horizontal cross section area of the p type layer 12 which is a lower portion is obtained.
The side surfaces of the p type layer 12 and the n type layer 11 are exposed by dry etching. Thus, in order to avoid short circuit between the layers, it is necessary to cover the side surfaces of the p type layer and the n type layer 11 with an insulating protective film 40. In order to secure the adhesiveness of the insulating protective film 40, the p type layer 12, and the n type layer 11, it is necessary to use a substance having a high adhesiveness with the insulating protective film 40 for the conductive layers 122 and 123. In FIG. 10, the conductive layers 122 and 123 and the solder layer 125 are formed in such a manner as not to block the air vent tr.
As prior arts of the invention, publications of the prior applications by the present applicant are mentioned as Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2008-186959) and Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2005-109432).